<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>i3c: xi3c_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">i3c
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
      <li><a href="pages.html"><span>Examples</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xi3c__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">xi3c_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga3f42f6b73f1536013fce8bef9a8b089c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3f42f6b73f1536013fce8bef9a8b089c">XI3C_HW_H_</a></td></tr>
<tr class="memdesc:ga3f42f6b73f1536013fce8bef9a8b089c"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="group___overview.html#ga3f42f6b73f1536013fce8bef9a8b089c">More...</a><br/></td></tr>
<tr class="separator:ga3f42f6b73f1536013fce8bef9a8b089c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1cd52261485c5865d5b0ff1fc16e9fa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1cd52261485c5865d5b0ff1fc16e9fa9">XI3C_BASEADDR</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:ga1cd52261485c5865d5b0ff1fc16e9fa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI_I3C0 Base Address #define XI3C_BASEADDR 0x80000000.  <a href="group___overview.html#ga1cd52261485c5865d5b0ff1fc16e9fa9">More...</a><br/></td></tr>
<tr class="separator:ga1cd52261485c5865d5b0ff1fc16e9fa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader"></div></td></tr>
<tr class="memitem:gaa938ff976973faa16dd719be03700422"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa938ff976973faa16dd719be03700422">XI3C_VERSION_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gaa938ff976973faa16dd719be03700422"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register offsets for the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> device.  <a href="group___overview.html#gaa938ff976973faa16dd719be03700422">More...</a><br/></td></tr>
<tr class="separator:gaa938ff976973faa16dd719be03700422"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeeafc8dc6cd85b8ecc8af8d545efa2d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaeeafc8dc6cd85b8ecc8af8d545efa2d6">XI3C_RESET_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gaeeafc8dc6cd85b8ecc8af8d545efa2d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset Register.  <a href="group___overview.html#gaeeafc8dc6cd85b8ecc8af8d545efa2d6">More...</a><br/></td></tr>
<tr class="separator:gaeeafc8dc6cd85b8ecc8af8d545efa2d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5098e75930c837ad7cd5445535e4d283"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5098e75930c837ad7cd5445535e4d283">XI3C_CR_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga5098e75930c837ad7cd5445535e4d283"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group___overview.html#ga5098e75930c837ad7cd5445535e4d283">More...</a><br/></td></tr>
<tr class="separator:ga5098e75930c837ad7cd5445535e4d283"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga201dee1806c408efbdf074cec11e02a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a>&#160;&#160;&#160;0x0C</td></tr>
<tr class="memdesc:ga201dee1806c408efbdf074cec11e02a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Address Register.  <a href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">More...</a><br/></td></tr>
<tr class="separator:ga201dee1806c408efbdf074cec11e02a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a3b3b24854197b7342e82f6d472ad60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga0a3b3b24854197b7342e82f6d472ad60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">More...</a><br/></td></tr>
<tr class="separator:ga0a3b3b24854197b7342e82f6d472ad60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8db15484dd9ba5bbfcd041249b63ef4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8db15484dd9ba5bbfcd041249b63ef4c">XI3C_INTR_STATUS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga8db15484dd9ba5bbfcd041249b63ef4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Event Register.  <a href="group___overview.html#ga8db15484dd9ba5bbfcd041249b63ef4c">More...</a><br/></td></tr>
<tr class="separator:ga8db15484dd9ba5bbfcd041249b63ef4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eca8a991fb3151108c6933bfeb51c5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:ga4eca8a991fb3151108c6933bfeb51c5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Event Enable(Rising Edge) Register.  <a href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">More...</a><br/></td></tr>
<tr class="separator:ga4eca8a991fb3151108c6933bfeb51c5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga342ba5ba87f55302937c4b128f10f9da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:ga342ba5ba87f55302937c4b128f10f9da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Event Enable(Falling Edge) Register.  <a href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">More...</a><br/></td></tr>
<tr class="separator:ga342ba5ba87f55302937c4b128f10f9da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga310ed8a56b21fca347c2cc0b3aa7f2f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga310ed8a56b21fca347c2cc0b3aa7f2f9">XI3C_CMD_FIFO_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga310ed8a56b21fca347c2cc0b3aa7f2f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Command FIFO Register.  <a href="group___overview.html#ga310ed8a56b21fca347c2cc0b3aa7f2f9">More...</a><br/></td></tr>
<tr class="separator:ga310ed8a56b21fca347c2cc0b3aa7f2f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38756ab021295465c1b621deb8d80ec2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga38756ab021295465c1b621deb8d80ec2">XI3C_WR_FIFO_OFFSET</a>&#160;&#160;&#160;0x24</td></tr>
<tr class="memdesc:ga38756ab021295465c1b621deb8d80ec2"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Write Data FIFO Register.  <a href="group___overview.html#ga38756ab021295465c1b621deb8d80ec2">More...</a><br/></td></tr>
<tr class="separator:ga38756ab021295465c1b621deb8d80ec2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c">XI3C_RD_FIFO_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Read Data FIFO Register.  <a href="group___overview.html#gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c">More...</a><br/></td></tr>
<tr class="separator:gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c063c7296db1c51db465c7e3609a8ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2c063c7296db1c51db465c7e3609a8ac">XI3C_RESP_STATUS_FIFO_OFFSET</a>&#160;&#160;&#160;0x2C</td></tr>
<tr class="memdesc:ga2c063c7296db1c51db465c7e3609a8ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Response status FIFO Register.  <a href="group___overview.html#ga2c063c7296db1c51db465c7e3609a8ac">More...</a><br/></td></tr>
<tr class="separator:ga2c063c7296db1c51db465c7e3609a8ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d2708084fb73a3e790473dcd71a8b46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">XI3C_FIFO_LVL_STATUS_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:ga2d2708084fb73a3e790473dcd71a8b46"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C CMD &amp; WR FIFO LVL Register.  <a href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">More...</a><br/></td></tr>
<tr class="separator:ga2d2708084fb73a3e790473dcd71a8b46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga699026be01649fea70621f96ab6f8dec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">XI3C_FIFO_LVL_STATUS_1_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga699026be01649fea70621f96ab6f8dec"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C RESP &amp; RD FIFO LVL Register.  <a href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">More...</a><br/></td></tr>
<tr class="separator:ga699026be01649fea70621f96ab6f8dec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19907a1f8fccab4045cec4f33a0a019b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga19907a1f8fccab4045cec4f33a0a019b"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C SCL HIGH Register.  <a href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">More...</a><br/></td></tr>
<tr class="separator:ga19907a1f8fccab4045cec4f33a0a019b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacac5bc3663c87ed53678bbb88c58a737"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:gacac5bc3663c87ed53678bbb88c58a737"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C SCL LOW Register.  <a href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">More...</a><br/></td></tr>
<tr class="separator:gacac5bc3663c87ed53678bbb88c58a737"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac98f0b52e9c9c40ccf5b41cd8fce94d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:gac98f0b52e9c9c40ccf5b41cd8fce94d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C SDA HOLD Register.  <a href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">More...</a><br/></td></tr>
<tr class="separator:gac98f0b52e9c9c40ccf5b41cd8fce94d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5eceedf78b84fdf70668668722c671af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">XI3C_BUS_IDLE_OFFSET</a>&#160;&#160;&#160;0x44</td></tr>
<tr class="memdesc:ga5eceedf78b84fdf70668668722c671af"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C CONTROLLER BUS IDLE Register.  <a href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">More...</a><br/></td></tr>
<tr class="separator:ga5eceedf78b84fdf70668668722c671af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad8bc7285bee2d4b07caf0be75751909"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a>&#160;&#160;&#160;0x48</td></tr>
<tr class="memdesc:gaad8bc7285bee2d4b07caf0be75751909"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C START SETUP Register.  <a href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">More...</a><br/></td></tr>
<tr class="separator:gaad8bc7285bee2d4b07caf0be75751909"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b6019d7d90a6ffe16d5031c677da546"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a>&#160;&#160;&#160;0x4C</td></tr>
<tr class="memdesc:ga7b6019d7d90a6ffe16d5031c677da546"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C START HOLD Register.  <a href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">More...</a><br/></td></tr>
<tr class="separator:ga7b6019d7d90a6ffe16d5031c677da546"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9c766c72c30099de526c5d78a99ba5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a>&#160;&#160;&#160;0x50</td></tr>
<tr class="memdesc:gaf9c766c72c30099de526c5d78a99ba5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C STOP Setup Register.  <a href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">More...</a><br/></td></tr>
<tr class="separator:gaf9c766c72c30099de526c5d78a99ba5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71c271412e577611810fe80fe0f51703"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a>&#160;&#160;&#160;0x54</td></tr>
<tr class="memdesc:ga71c271412e577611810fe80fe0f51703"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C OD SCL HIGH Register.  <a href="group___overview.html#ga71c271412e577611810fe80fe0f51703">More...</a><br/></td></tr>
<tr class="separator:ga71c271412e577611810fe80fe0f51703"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5455e0616c1f4d0728b493ea0fb92b6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga5455e0616c1f4d0728b493ea0fb92b6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C OD SCL LOW Register.  <a href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">More...</a><br/></td></tr>
<tr class="separator:ga5455e0616c1f4d0728b493ea0fb92b6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c64e1b8520dbdc358d94d36c3927256"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4c64e1b8520dbdc358d94d36c3927256">XI3C_TARGET_ADDR_BCR</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga4c64e1b8520dbdc358d94d36c3927256"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Target dynamic Address and BCR Register.  <a href="group___overview.html#ga4c64e1b8520dbdc358d94d36c3927256">More...</a><br/></td></tr>
<tr class="separator:ga4c64e1b8520dbdc358d94d36c3927256"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga698dbf261cef62aea0e39e26e36444dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">XI3C_MWL_MRL</a>&#160;&#160;&#160;0x74</td></tr>
<tr class="memdesc:ga698dbf261cef62aea0e39e26e36444dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Write and Max Read length.  <a href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">More...</a><br/></td></tr>
<tr class="separator:ga698dbf261cef62aea0e39e26e36444dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga211c542ff6c1ff32dbf288967d17d38a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga211c542ff6c1ff32dbf288967d17d38a">XI3C_EVENT</a>&#160;&#160;&#160;0x78</td></tr>
<tr class="memdesc:ga211c542ff6c1ff32dbf288967d17d38a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target events.  <a href="group___overview.html#ga211c542ff6c1ff32dbf288967d17d38a">More...</a><br/></td></tr>
<tr class="separator:ga211c542ff6c1ff32dbf288967d17d38a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6f648bc7840eb8d61cb3c5d06d3f613"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab6f648bc7840eb8d61cb3c5d06d3f613">XI3C_GETMXDS</a>&#160;&#160;&#160;0x80</td></tr>
<tr class="memdesc:gab6f648bc7840eb8d61cb3c5d06d3f613"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device Max Data Speed.  <a href="group___overview.html#gab6f648bc7840eb8d61cb3c5d06d3f613">More...</a><br/></td></tr>
<tr class="separator:gab6f648bc7840eb8d61cb3c5d06d3f613"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6da19b220a65d5ada6af1c9962d27184"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6da19b220a65d5ada6af1c9962d27184">XI3C_GETSTATUS</a>&#160;&#160;&#160;0x84</td></tr>
<tr class="memdesc:ga6da19b220a65d5ada6af1c9962d27184"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device current Status.  <a href="group___overview.html#ga6da19b220a65d5ada6af1c9962d27184">More...</a><br/></td></tr>
<tr class="separator:ga6da19b220a65d5ada6af1c9962d27184"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadeb959adfc801c98b78b2efa8fc09f8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadeb959adfc801c98b78b2efa8fc09f8b">XI3C_GETCAPS_REG0</a>&#160;&#160;&#160;0x88</td></tr>
<tr class="memdesc:gadeb959adfc801c98b78b2efa8fc09f8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device Format 1 Capabilities.  <a href="group___overview.html#gadeb959adfc801c98b78b2efa8fc09f8b">More...</a><br/></td></tr>
<tr class="separator:gadeb959adfc801c98b78b2efa8fc09f8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3a5ef5be5a8d1b70ce3fb3da4620c04f">XI3C_GETCAPS_REG1</a>&#160;&#160;&#160;0x8c</td></tr>
<tr class="memdesc:ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device Format 2 Capabilities.  <a href="group___overview.html#ga3a5ef5be5a8d1b70ce3fb3da4620c04f">More...</a><br/></td></tr>
<tr class="separator:ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga459c04dba1fbcb734de88d489013acb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga459c04dba1fbcb734de88d489013acb6">XI3C_CON_RD_BYTE_COUNT</a>&#160;&#160;&#160;0x90</td></tr>
<tr class="memdesc:ga459c04dba1fbcb734de88d489013acb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read byte count register.  <a href="group___overview.html#ga459c04dba1fbcb734de88d489013acb6">More...</a><br/></td></tr>
<tr class="separator:ga459c04dba1fbcb734de88d489013acb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Version Register mask(s)</div></td></tr>
<tr class="memitem:ga841758673758b882ccbf9d63d2989776"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga841758673758b882ccbf9d63d2989776">XI3C_INTERNAL_REVISION_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga841758673758b882ccbf9d63d2989776"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 3:0 - Internal revision.  <a href="group___overview.html#ga841758673758b882ccbf9d63d2989776">More...</a><br/></td></tr>
<tr class="separator:ga841758673758b882ccbf9d63d2989776"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d02cd501c9e204b141ff17882b0f78e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4d02cd501c9e204b141ff17882b0f78e">XI3C_CORE_PATCH_REVISION_MASK</a>&#160;&#160;&#160;0x000000F0</td></tr>
<tr class="memdesc:ga4d02cd501c9e204b141ff17882b0f78e"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 7:4 - Patch revision.  <a href="group___overview.html#ga4d02cd501c9e204b141ff17882b0f78e">More...</a><br/></td></tr>
<tr class="separator:ga4d02cd501c9e204b141ff17882b0f78e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a330fc6ac05e41f3e3c13b60ff74c8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a330fc6ac05e41f3e3c13b60ff74c8f">XI3C_CORE_REVISION_NUM_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:ga9a330fc6ac05e41f3e3c13b60ff74c8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 15:8 - Revision number.  <a href="group___overview.html#ga9a330fc6ac05e41f3e3c13b60ff74c8f">More...</a><br/></td></tr>
<tr class="separator:ga9a330fc6ac05e41f3e3c13b60ff74c8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffdb23d9d4f9825efe1089262b5084e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaffdb23d9d4f9825efe1089262b5084e3">XI3C_CORE_VERSION_MINOR_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gaffdb23d9d4f9825efe1089262b5084e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 23:16 - Minor version.  <a href="group___overview.html#gaffdb23d9d4f9825efe1089262b5084e3">More...</a><br/></td></tr>
<tr class="separator:gaffdb23d9d4f9825efe1089262b5084e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3779fb2a8e036ac0bb9f80f7fd150c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf3779fb2a8e036ac0bb9f80f7fd150c7">XI3C_CORE_VERSION_MAJOR_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:gaf3779fb2a8e036ac0bb9f80f7fd150c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 31:24 - Major version.  <a href="group___overview.html#gaf3779fb2a8e036ac0bb9f80f7fd150c7">More...</a><br/></td></tr>
<tr class="separator:gaf3779fb2a8e036ac0bb9f80f7fd150c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaacd2bda9c2e5bd357c5fdee8ed2c8614"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaacd2bda9c2e5bd357c5fdee8ed2c8614">XI3C_CORE_REVISION_NUM_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gaacd2bda9c2e5bd357c5fdee8ed2c8614"><td class="mdescLeft">&#160;</td><td class="mdescRight">Revision number shift.  <a href="group___overview.html#gaacd2bda9c2e5bd357c5fdee8ed2c8614">More...</a><br/></td></tr>
<tr class="separator:gaacd2bda9c2e5bd357c5fdee8ed2c8614"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Reset Register mask(s)</div></td></tr>
<tr class="memitem:ga1da2b90b0f8ce89043634891a7e9ba49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1da2b90b0f8ce89043634891a7e9ba49">XI3C_SOFT_RESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga1da2b90b0f8ce89043634891a7e9ba49"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Reset.  <a href="group___overview.html#ga1da2b90b0f8ce89043634891a7e9ba49">More...</a><br/></td></tr>
<tr class="separator:ga1da2b90b0f8ce89043634891a7e9ba49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b5681e77e2c8502b4a0ae46df3a4b26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0b5681e77e2c8502b4a0ae46df3a4b26">XI3C_CMD_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga0b5681e77e2c8502b4a0ae46df3a4b26"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Cmd fifo reset.  <a href="group___overview.html#ga0b5681e77e2c8502b4a0ae46df3a4b26">More...</a><br/></td></tr>
<tr class="separator:ga0b5681e77e2c8502b4a0ae46df3a4b26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8813d9d73c5f1c95bc5867d60b829d6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8813d9d73c5f1c95bc5867d60b829d6d">XI3C_WR_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga8813d9d73c5f1c95bc5867d60b829d6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Write fifo reset.  <a href="group___overview.html#ga8813d9d73c5f1c95bc5867d60b829d6d">More...</a><br/></td></tr>
<tr class="separator:ga8813d9d73c5f1c95bc5867d60b829d6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c07229c964da96edd30443b424def69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0c07229c964da96edd30443b424def69">XI3C_RD_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga0c07229c964da96edd30443b424def69"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Read fifo reset.  <a href="group___overview.html#ga0c07229c964da96edd30443b424def69">More...</a><br/></td></tr>
<tr class="separator:ga0c07229c964da96edd30443b424def69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacadbf79a1e643cce18a063a2289a1105"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacadbf79a1e643cce18a063a2289a1105">XI3C_RESP_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gacadbf79a1e643cce18a063a2289a1105"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Response fifo reset.  <a href="group___overview.html#gacadbf79a1e643cce18a063a2289a1105">More...</a><br/></td></tr>
<tr class="separator:gacadbf79a1e643cce18a063a2289a1105"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7a35f2e6a12487ef3dd2efa5e8f1992"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac7a35f2e6a12487ef3dd2efa5e8f1992">XI3C_ALL_FIFOS_RESET_MASK</a>&#160;&#160;&#160;0x0000001E</td></tr>
<tr class="memdesc:gac7a35f2e6a12487ef3dd2efa5e8f1992"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 to 4 - All fifos reset.  <a href="group___overview.html#gac7a35f2e6a12487ef3dd2efa5e8f1992">More...</a><br/></td></tr>
<tr class="separator:gac7a35f2e6a12487ef3dd2efa5e8f1992"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register (CR) mask(s)</div></td></tr>
<tr class="memitem:ga73562c3dd852ad953028edba3fc73184"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga73562c3dd852ad953028edba3fc73184">XI3C_CR_EN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga73562c3dd852ad953028edba3fc73184"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Core Enable.  <a href="group___overview.html#ga73562c3dd852ad953028edba3fc73184">More...</a><br/></td></tr>
<tr class="separator:ga73562c3dd852ad953028edba3fc73184"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaebe1db8ec816daf035299f26c0d3f98c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaebe1db8ec816daf035299f26c0d3f98c">XI3C_CR_ABORT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaebe1db8ec816daf035299f26c0d3f98c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Abort Transaction.  <a href="group___overview.html#gaebe1db8ec816daf035299f26c0d3f98c">More...</a><br/></td></tr>
<tr class="separator:gaebe1db8ec816daf035299f26c0d3f98c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a05227ca83f5c2a8d5a3b2b5f2683ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4a05227ca83f5c2a8d5a3b2b5f2683ec">XI3C_CR_RESUME_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga4a05227ca83f5c2a8d5a3b2b5f2683ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Resume Operation.  <a href="group___overview.html#ga4a05227ca83f5c2a8d5a3b2b5f2683ec">More...</a><br/></td></tr>
<tr class="separator:ga4a05227ca83f5c2a8d5a3b2b5f2683ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7aa5b9b25b40b6024fdd46c497a5761c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7aa5b9b25b40b6024fdd46c497a5761c">XI3C_CR_IBI_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga7aa5b9b25b40b6024fdd46c497a5761c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - IBI Enable.  <a href="group___overview.html#ga7aa5b9b25b40b6024fdd46c497a5761c">More...</a><br/></td></tr>
<tr class="separator:ga7aa5b9b25b40b6024fdd46c497a5761c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26058f3049f96576501e4f6ca90de762"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga26058f3049f96576501e4f6ca90de762">XI3C_CR_HJ_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga26058f3049f96576501e4f6ca90de762"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Hot Join Enable.  <a href="group___overview.html#ga26058f3049f96576501e4f6ca90de762">More...</a><br/></td></tr>
<tr class="separator:ga26058f3049f96576501e4f6ca90de762"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c6e38927f17536cb4cb8676d32c0d98"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6c6e38927f17536cb4cb8676d32c0d98">XI3C_CR_ACCEPT_CTRL_ROLE_REQ</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6c6e38927f17536cb4cb8676d32c0d98"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Generate ACK for secondary controller role request IBI.  <a href="group___overview.html#ga6c6e38927f17536cb4cb8676d32c0d98">More...</a><br/></td></tr>
<tr class="separator:ga6c6e38927f17536cb4cb8676d32c0d98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register (SR) mask(s)</div></td></tr>
<tr class="memitem:ga07f073cf0ff84797b4d805541b4fbec7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga07f073cf0ff84797b4d805541b4fbec7">XI3C_SR_BUS_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga07f073cf0ff84797b4d805541b4fbec7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Bus Busy.  <a href="group___overview.html#ga07f073cf0ff84797b4d805541b4fbec7">More...</a><br/></td></tr>
<tr class="separator:ga07f073cf0ff84797b4d805541b4fbec7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59481855d3ba5232e103325915b8c9c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga59481855d3ba5232e103325915b8c9c9">XI3C_SR_CLK_STALL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga59481855d3ba5232e103325915b8c9c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Clock Stall.  <a href="group___overview.html#ga59481855d3ba5232e103325915b8c9c9">More...</a><br/></td></tr>
<tr class="separator:ga59481855d3ba5232e103325915b8c9c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga734f3b7a052444daaed24d346b67cd43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga734f3b7a052444daaed24d346b67cd43">XI3C_SR_CMD_FULL_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga734f3b7a052444daaed24d346b67cd43"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Cmd Fifo Full.  <a href="group___overview.html#ga734f3b7a052444daaed24d346b67cd43">More...</a><br/></td></tr>
<tr class="separator:ga734f3b7a052444daaed24d346b67cd43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3374e03a2587e874036d2f516a7de67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab3374e03a2587e874036d2f516a7de67">XI3C_SR_RESP_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gab3374e03a2587e874036d2f516a7de67"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Resp Fifo Full.  <a href="group___overview.html#gab3374e03a2587e874036d2f516a7de67">More...</a><br/></td></tr>
<tr class="separator:gab3374e03a2587e874036d2f516a7de67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9b9816a95d893384063e7fe2ce892ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">XI3C_SR_RESP_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gac9b9816a95d893384063e7fe2ce892ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Resp Fifo not empty.  <a href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">More...</a><br/></td></tr>
<tr class="separator:gac9b9816a95d893384063e7fe2ce892ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab8e7f9751ccb9a2bc60cbf3ef63ec5fe">XI3C_SR_WR_FULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Write Fifo Full.  <a href="group___overview.html#gab8e7f9751ccb9a2bc60cbf3ef63ec5fe">More...</a><br/></td></tr>
<tr class="separator:gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb62f870d6eaf9a0e84455a3b8f95802"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabb62f870d6eaf9a0e84455a3b8f95802">XI3C_SR_RD_FULL_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gabb62f870d6eaf9a0e84455a3b8f95802"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 6 - Read Fifo Full.  <a href="group___overview.html#gabb62f870d6eaf9a0e84455a3b8f95802">More...</a><br/></td></tr>
<tr class="separator:gabb62f870d6eaf9a0e84455a3b8f95802"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga036ea1c62d3f28a118f5dcd137c128e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga036ea1c62d3f28a118f5dcd137c128e2">XI3C_SR_IBI_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga036ea1c62d3f28a118f5dcd137c128e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 7 - IBI.  <a href="group___overview.html#ga036ea1c62d3f28a118f5dcd137c128e2">More...</a><br/></td></tr>
<tr class="separator:ga036ea1c62d3f28a118f5dcd137c128e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6c4dfdb3896048df2fe69d50d72f081"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab6c4dfdb3896048df2fe69d50d72f081">XI3C_SR_HJ_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gab6c4dfdb3896048df2fe69d50d72f081"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 8 - Hot join.  <a href="group___overview.html#gab6c4dfdb3896048df2fe69d50d72f081">More...</a><br/></td></tr>
<tr class="separator:gab6c4dfdb3896048df2fe69d50d72f081"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28fcad7bbd4d188d5f7115fc9a6c124a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga28fcad7bbd4d188d5f7115fc9a6c124a">XI3C_SR_CTRL_ROLE_REQUEST_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga28fcad7bbd4d188d5f7115fc9a6c124a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 9 - Received control role request.  <a href="group___overview.html#ga28fcad7bbd4d188d5f7115fc9a6c124a">More...</a><br/></td></tr>
<tr class="separator:ga28fcad7bbd4d188d5f7115fc9a6c124a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72bccabb2e243917849140d2fa491bd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga72bccabb2e243917849140d2fa491bd7">XI3C_SR_ERROR_TYPE_CE3_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga72bccabb2e243917849140d2fa491bd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role.  <a href="group___overview.html#ga72bccabb2e243917849140d2fa491bd7">More...</a><br/></td></tr>
<tr class="separator:ga72bccabb2e243917849140d2fa491bd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79bae274f84eac816db1b3abc42aae5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga79bae274f84eac816db1b3abc42aae5c">XI3C_SR_RETURN_ROLE_REQ_ACK_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga79bae274f84eac816db1b3abc42aae5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 11 - Received ACK on controller role request back.  <a href="group___overview.html#ga79bae274f84eac816db1b3abc42aae5c">More...</a><br/></td></tr>
<tr class="separator:ga79bae274f84eac816db1b3abc42aae5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae32d0edcf3609f4aa31a8385861d6f00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae32d0edcf3609f4aa31a8385861d6f00">XI3C_SR_RD_FIFO_ALMOST_FULL_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:gae32d0edcf3609f4aa31a8385861d6f00"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 12 - Read Fifo almost Full.  <a href="group___overview.html#gae32d0edcf3609f4aa31a8385861d6f00">More...</a><br/></td></tr>
<tr class="separator:gae32d0edcf3609f4aa31a8385861d6f00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga081fe15e4db5cd138cb5a79161530726"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga081fe15e4db5cd138cb5a79161530726">XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:ga081fe15e4db5cd138cb5a79161530726"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 13 - CMD FIFO empty.  <a href="group___overview.html#ga081fe15e4db5cd138cb5a79161530726">More...</a><br/></td></tr>
<tr class="separator:ga081fe15e4db5cd138cb5a79161530726"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaddc84e40ea7fbdede29fc1d687d31c82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaddc84e40ea7fbdede29fc1d687d31c82">XI3C_SR_WR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gaddc84e40ea7fbdede29fc1d687d31c82"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 14 - Write FIFO empty.  <a href="group___overview.html#gaddc84e40ea7fbdede29fc1d687d31c82">More...</a><br/></td></tr>
<tr class="separator:gaddc84e40ea7fbdede29fc1d687d31c82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga921e87b7a626211a1983b98dc3b22977"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">XI3C_SR_RD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga921e87b7a626211a1983b98dc3b22977"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 15 - Read FIFO empty.  <a href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">More...</a><br/></td></tr>
<tr class="separator:ga921e87b7a626211a1983b98dc3b22977"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e4d65a8da33e49fda2aeba47497ab6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7e4d65a8da33e49fda2aeba47497ab6a">XI3C_SR_SLV_DYNC_ADDR_DONE_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga7e4d65a8da33e49fda2aeba47497ab6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 19 - Dynamic address assigned to slave.  <a href="group___overview.html#ga7e4d65a8da33e49fda2aeba47497ab6a">More...</a><br/></td></tr>
<tr class="separator:ga7e4d65a8da33e49fda2aeba47497ab6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register (SR) Shifts(s)</div></td></tr>
<tr class="memitem:ga757f54fcb43fbdfe0ade99df244a68a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga757f54fcb43fbdfe0ade99df244a68a7">XI3C_SR_BUS_BUSY_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga757f54fcb43fbdfe0ade99df244a68a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Bus Busy.  <a href="group___overview.html#ga757f54fcb43fbdfe0ade99df244a68a7">More...</a><br/></td></tr>
<tr class="separator:ga757f54fcb43fbdfe0ade99df244a68a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c649b5952826e117e67f92d4aee240a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6c649b5952826e117e67f92d4aee240a">XI3C_SR_CLK_STALL_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga6c649b5952826e117e67f92d4aee240a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Clock Stall.  <a href="group___overview.html#ga6c649b5952826e117e67f92d4aee240a">More...</a><br/></td></tr>
<tr class="separator:ga6c649b5952826e117e67f92d4aee240a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1869fb29215628f67e0a0414eee54d0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1869fb29215628f67e0a0414eee54d0e">XI3C_SR_CMD_FULL_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga1869fb29215628f67e0a0414eee54d0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Cmd Fifo Full.  <a href="group___overview.html#ga1869fb29215628f67e0a0414eee54d0e">More...</a><br/></td></tr>
<tr class="separator:ga1869fb29215628f67e0a0414eee54d0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdbb91c4f4f0bad0b9a1c43ff32d9d34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafdbb91c4f4f0bad0b9a1c43ff32d9d34">XI3C_SR_RESP_FULL_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gafdbb91c4f4f0bad0b9a1c43ff32d9d34"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Resp Fifo Full.  <a href="group___overview.html#gafdbb91c4f4f0bad0b9a1c43ff32d9d34">More...</a><br/></td></tr>
<tr class="separator:gafdbb91c4f4f0bad0b9a1c43ff32d9d34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77ec3c78d800fc0a33781122c40fb8b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga77ec3c78d800fc0a33781122c40fb8b8">XI3C_SR_RESP_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga77ec3c78d800fc0a33781122c40fb8b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Resp Fifo not empty.  <a href="group___overview.html#ga77ec3c78d800fc0a33781122c40fb8b8">More...</a><br/></td></tr>
<tr class="separator:ga77ec3c78d800fc0a33781122c40fb8b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9453d2e836832225cdb9166fbf2a509b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9453d2e836832225cdb9166fbf2a509b">XI3C_SR_WR_FULL_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga9453d2e836832225cdb9166fbf2a509b"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Write Fifo Full.  <a href="group___overview.html#ga9453d2e836832225cdb9166fbf2a509b">More...</a><br/></td></tr>
<tr class="separator:ga9453d2e836832225cdb9166fbf2a509b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ab43aee70ecb74f43a04a2b4288c5ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5ab43aee70ecb74f43a04a2b4288c5ef">XI3C_SR_RD_FULL_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga5ab43aee70ecb74f43a04a2b4288c5ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 6 - Read Fifo Full.  <a href="group___overview.html#ga5ab43aee70ecb74f43a04a2b4288c5ef">More...</a><br/></td></tr>
<tr class="separator:ga5ab43aee70ecb74f43a04a2b4288c5ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga505303ab58a602428e0f9f4236c48b3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga505303ab58a602428e0f9f4236c48b3b">XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ga505303ab58a602428e0f9f4236c48b3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 19 - Dynamic address assigned to slave.  <a href="group___overview.html#ga505303ab58a602428e0f9f4236c48b3b">More...</a><br/></td></tr>
<tr class="separator:ga505303ab58a602428e0f9f4236c48b3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">response and other mask(s)</div></td></tr>
<tr class="memitem:ga017f74b7be35475e374ccc4f8b9a5552"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga017f74b7be35475e374ccc4f8b9a5552"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_ID_MASK</b>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="separator:ga017f74b7be35475e374ccc4f8b9a5552"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac404bcf661ead5290c873291d0142765"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac404bcf661ead5290c873291d0142765"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_RW_MASK</b>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="separator:gac404bcf661ead5290c873291d0142765"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8befc05a5540da548a349678c621e78f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8befc05a5540da548a349678c621e78f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_CODE_MASK</b>&#160;&#160;&#160;0x000001E0</td></tr>
<tr class="separator:ga8befc05a5540da548a349678c621e78f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a6655dd9e46f36b9208cfce407b34ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8a6655dd9e46f36b9208cfce407b34ad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_BYTES_MASK</b>&#160;&#160;&#160;0x001FFE00</td></tr>
<tr class="separator:ga8a6655dd9e46f36b9208cfce407b34ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2f7e3d67a606869e767cf5d05c0d8fd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae2f7e3d67a606869e767cf5d05c0d8fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_CCC_MASK</b>&#160;&#160;&#160;0x1FE00000</td></tr>
<tr class="separator:gae2f7e3d67a606869e767cf5d05c0d8fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6de7f6e6bb570f4775dc76469f030062"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6de7f6e6bb570f4775dc76469f030062"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_7E_FRAME_MASK</b>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="separator:ga6de7f6e6bb570f4775dc76469f030062"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1938a386a2f3c813b05d2d4f6f211a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf1938a386a2f3c813b05d2d4f6f211a2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MRL_MASK</b>&#160;&#160;&#160;0x0FFF0000</td></tr>
<tr class="separator:gaf1938a386a2f3c813b05d2d4f6f211a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa368f13aed4734e541d74056af2d4e52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa368f13aed4734e541d74056af2d4e52"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GRP_ADDR_MASK</b>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="separator:gaa368f13aed4734e541d74056af2d4e52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">response and other shift(s)</div></td></tr>
<tr class="memitem:gaa68362596244862289a0ecdecb713b24"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa68362596244862289a0ecdecb713b24"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_TID_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:gaa68362596244862289a0ecdecb713b24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadde031c205995e6919531d6db852892b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadde031c205995e6919531d6db852892b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_RW_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:gadde031c205995e6919531d6db852892b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ded0321062d14b59702b9c84b8272ce"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ded0321062d14b59702b9c84b8272ce"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_CODE_SHIFT</b>&#160;&#160;&#160;5</td></tr>
<tr class="separator:ga1ded0321062d14b59702b9c84b8272ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2dd6bd969d456e60451062c88f1a7f06"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2dd6bd969d456e60451062c88f1a7f06"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_BYTES_SHIFT</b>&#160;&#160;&#160;9</td></tr>
<tr class="separator:ga2dd6bd969d456e60451062c88f1a7f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac09786b36a4c9097f223c4cc54f77227"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac09786b36a4c9097f223c4cc54f77227"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_LVL_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gac09786b36a4c9097f223c4cc54f77227"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4c08a7a7b54c88b641328fb97eb72c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad4c08a7a7b54c88b641328fb97eb72c7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_CCC_SHIFT</b>&#160;&#160;&#160;21</td></tr>
<tr class="separator:gad4c08a7a7b54c88b641328fb97eb72c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1f141082803c7b2b9bd1d98f9ec3e5e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae1f141082803c7b2b9bd1d98f9ec3e5e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_7E_FRAME_SHIFT</b>&#160;&#160;&#160;29</td></tr>
<tr class="separator:gae1f141082803c7b2b9bd1d98f9ec3e5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb7531d55c7bbb07f52902688a0e1fbe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb7531d55c7bbb07f52902688a0e1fbe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CMD_LVL_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gabb7531d55c7bbb07f52902688a0e1fbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ddc10a02fad8b842d5f0cd41d4c513a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7ddc10a02fad8b842d5f0cd41d4c513a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MRL_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga7ddc10a02fad8b842d5f0cd41d4c513a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0789923e9c8a476df3377e1a2d0b981f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0789923e9c8a476df3377e1a2d0b981f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MWL_MRL_MSB_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:ga0789923e9c8a476df3377e1a2d0b981f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf55e388caa732df79e7dc38339548db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacf55e388caa732df79e7dc38339548db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GRP_ADDR_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:gacf55e388caa732df79e7dc38339548db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf900d5ea8aedc5cd5223081dc9f8b62"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacf900d5ea8aedc5cd5223081dc9f8b62"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GETSTATUS_FORMAT2_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gacf900d5ea8aedc5cd5223081dc9f8b62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga57b26791795ff6191568fdeea15e217b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga57b26791795ff6191568fdeea15e217b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GETMXDS_FORMAT3_DATA_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga57b26791795ff6191568fdeea15e217b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga507f769cc96f4e2e2419cd51479a5c83"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga507f769cc96f4e2e2419cd51479a5c83"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CAPS4_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:ga507f769cc96f4e2e2419cd51479a5c83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga157aa36ab6c5be15558175de9b6156fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga157aa36ab6c5be15558175de9b6156fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CAPS3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga157aa36ab6c5be15558175de9b6156fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fb63998f8659403b87b5c7681808136"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1fb63998f8659403b87b5c7681808136"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CAPS2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:ga1fb63998f8659403b87b5c7681808136"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">bit masks</div></td></tr>
<tr class="memitem:ga4b47e1b9ddabc39f962e090ea2b3f91d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b47e1b9ddabc39f962e090ea2b3f91d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_1BIT_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:ga4b47e1b9ddabc39f962e090ea2b3f91d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga977ed3d17a2a8610bef6256aff7bcc67"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga977ed3d17a2a8610bef6256aff7bcc67"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_2BITS_MASK</b>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="separator:ga977ed3d17a2a8610bef6256aff7bcc67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e8331f0ba00e9258cef4d75d75c35d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9e8331f0ba00e9258cef4d75d75c35d2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_3BITS_MASK</b>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="separator:ga9e8331f0ba00e9258cef4d75d75c35d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd57e2db48d26315c7ad4bb8a1db66a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd57e2db48d26315c7ad4bb8a1db66a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_4BITS_MASK</b>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="separator:gacd57e2db48d26315c7ad4bb8a1db66a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga762f1005e1dfe41b4e449367e7c5c8c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga762f1005e1dfe41b4e449367e7c5c8c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_5BITS_MASK</b>&#160;&#160;&#160;0x0000001F</td></tr>
<tr class="separator:ga762f1005e1dfe41b4e449367e7c5c8c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga701ea9916070dd7d0aaa3f6e5e2a7820"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga701ea9916070dd7d0aaa3f6e5e2a7820"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_6BITS_MASK</b>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="separator:ga701ea9916070dd7d0aaa3f6e5e2a7820"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga285b0d4729f80a9936c1d09379be8dde"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga285b0d4729f80a9936c1d09379be8dde"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_7BITS_MASK</b>&#160;&#160;&#160;0x0000007F</td></tr>
<tr class="separator:ga285b0d4729f80a9936c1d09379be8dde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga397f53e4bcf6a6e3f4a824de8810c1be"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga397f53e4bcf6a6e3f4a824de8810c1be"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_8BITS_MASK</b>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="separator:ga397f53e4bcf6a6e3f4a824de8810c1be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf15b3eb130b00eb66d1d0ca0334f63a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf15b3eb130b00eb66d1d0ca0334f63a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_9BITS_MASK</b>&#160;&#160;&#160;0x000001FF</td></tr>
<tr class="separator:gaf15b3eb130b00eb66d1d0ca0334f63a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae081d7edf96c90780f710f900d5efa4c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae081d7edf96c90780f710f900d5efa4c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_10BITS_MASK</b>&#160;&#160;&#160;0x000003FF</td></tr>
<tr class="separator:gae081d7edf96c90780f710f900d5efa4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c1adf8c4596376fa193901e2a5a0e97"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3c1adf8c4596376fa193901e2a5a0e97"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_11BITS_MASK</b>&#160;&#160;&#160;0x000007FF</td></tr>
<tr class="separator:ga3c1adf8c4596376fa193901e2a5a0e97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga591d62fa59f55a741375c0842cdaf88f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga591d62fa59f55a741375c0842cdaf88f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_12BITS_MASK</b>&#160;&#160;&#160;0x00000FFF</td></tr>
<tr class="separator:ga591d62fa59f55a741375c0842cdaf88f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f4a0140ca1eac008af8323e830ad633"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3f4a0140ca1eac008af8323e830ad633"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_13BITS_MASK</b>&#160;&#160;&#160;0x00001FFF</td></tr>
<tr class="separator:ga3f4a0140ca1eac008af8323e830ad633"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6c30a7d158b268f2f812eb2351274e3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf6c30a7d158b268f2f812eb2351274e3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_14BITS_MASK</b>&#160;&#160;&#160;0x00003FFF</td></tr>
<tr class="separator:gaf6c30a7d158b268f2f812eb2351274e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga855ebd66800aeb296676452641e0dbef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga855ebd66800aeb296676452641e0dbef"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_15BITS_MASK</b>&#160;&#160;&#160;0x00007FFF</td></tr>
<tr class="separator:ga855ebd66800aeb296676452641e0dbef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3751d8774e194f1f920499e944c68a6a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3751d8774e194f1f920499e944c68a6a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_16BITS_MASK</b>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="separator:ga3751d8774e194f1f920499e944c68a6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb38bcb247a0389ea72d90d18171ccd3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb38bcb247a0389ea72d90d18171ccd3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_17BITS_MASK</b>&#160;&#160;&#160;0x0001FFFF</td></tr>
<tr class="separator:gabb38bcb247a0389ea72d90d18171ccd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ef00bea4092a3eb096d4de51b69c403"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7ef00bea4092a3eb096d4de51b69c403"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_18BITS_MASK</b>&#160;&#160;&#160;0x0003FFFF</td></tr>
<tr class="separator:ga7ef00bea4092a3eb096d4de51b69c403"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6432fb32a8e65b5742747c198db8c7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad6432fb32a8e65b5742747c198db8c7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_19BITS_MASK</b>&#160;&#160;&#160;0x0007FFFF</td></tr>
<tr class="separator:gad6432fb32a8e65b5742747c198db8c7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3ef8804e728831f2c39414bd0861679"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3ef8804e728831f2c39414bd0861679"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_20BITS_MASK</b>&#160;&#160;&#160;0x000FFFFF</td></tr>
<tr class="separator:gac3ef8804e728831f2c39414bd0861679"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae058d3e89399d015dd43473ab583c8b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae058d3e89399d015dd43473ab583c8b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MSB_8BITS_MASK</b>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="separator:gae058d3e89399d015dd43473ab583c8b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga236040697b992343689b1c23443bba9c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga236040697b992343689b1c23443bba9c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MSB_16BITS_MASK</b>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="separator:ga236040697b992343689b1c23443bba9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">interrupt Register (INTR) mask(s)</div></td></tr>
<tr class="memitem:gadde46b07ce0d970404a2fcf853661409"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadde46b07ce0d970404a2fcf853661409">XI3C_INTR_BUS_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gadde46b07ce0d970404a2fcf853661409"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Bus Busy.  <a href="group___overview.html#gadde46b07ce0d970404a2fcf853661409">More...</a><br/></td></tr>
<tr class="separator:gadde46b07ce0d970404a2fcf853661409"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa09dbddd10e88620c2423f103d1bd4a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa09dbddd10e88620c2423f103d1bd4a0">XI3C_INTR_CLK_STALL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa09dbddd10e88620c2423f103d1bd4a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Clock Stall.  <a href="group___overview.html#gaa09dbddd10e88620c2423f103d1bd4a0">More...</a><br/></td></tr>
<tr class="separator:gaa09dbddd10e88620c2423f103d1bd4a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10332d7b77429e9058fdcabe099cce36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga10332d7b77429e9058fdcabe099cce36">XI3C_INTR_CMD_FULL_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga10332d7b77429e9058fdcabe099cce36"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Cmd Fifo Full.  <a href="group___overview.html#ga10332d7b77429e9058fdcabe099cce36">More...</a><br/></td></tr>
<tr class="separator:ga10332d7b77429e9058fdcabe099cce36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga070c1bd5720ca64e0a76e8afa6d6b0a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga070c1bd5720ca64e0a76e8afa6d6b0a6">XI3C_INTR_RESP_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga070c1bd5720ca64e0a76e8afa6d6b0a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Resp Fifo Full.  <a href="group___overview.html#ga070c1bd5720ca64e0a76e8afa6d6b0a6">More...</a><br/></td></tr>
<tr class="separator:ga070c1bd5720ca64e0a76e8afa6d6b0a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabdb31954696a689f6a99d67ec180e6e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gabdb31954696a689f6a99d67ec180e6e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Resp Fifo not empty.  <a href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">More...</a><br/></td></tr>
<tr class="separator:gabdb31954696a689f6a99d67ec180e6e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb00abdbc75747d0a18d1e8410d07a68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacb00abdbc75747d0a18d1e8410d07a68">XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gacb00abdbc75747d0a18d1e8410d07a68"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Write Fifo Full.  <a href="group___overview.html#gacb00abdbc75747d0a18d1e8410d07a68">More...</a><br/></td></tr>
<tr class="separator:gacb00abdbc75747d0a18d1e8410d07a68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0b74281de2f580f72138e92fa448244"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa0b74281de2f580f72138e92fa448244">XI3C_INTR_RD_FULL_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaa0b74281de2f580f72138e92fa448244"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 6 - Read Fifo Full.  <a href="group___overview.html#gaa0b74281de2f580f72138e92fa448244">More...</a><br/></td></tr>
<tr class="separator:gaa0b74281de2f580f72138e92fa448244"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6015ecb529e10d7ac6c6d431144242d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">XI3C_ALL_INTR_MASK</a>&#160;&#160;&#160;0x0000007F</td></tr>
<tr class="memdesc:ga6015ecb529e10d7ac6c6d431144242d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">6:0 BITS  <a href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">More...</a><br/></td></tr>
<tr class="separator:ga6015ecb529e10d7ac6c6d431144242d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaddf7bc2cde2b99f5f00b09c8e39f9a73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaddf7bc2cde2b99f5f00b09c8e39f9a73">XI3C_INTR_IBI_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gaddf7bc2cde2b99f5f00b09c8e39f9a73"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 7 - IBI.  <a href="group___overview.html#gaddf7bc2cde2b99f5f00b09c8e39f9a73">More...</a><br/></td></tr>
<tr class="separator:gaddf7bc2cde2b99f5f00b09c8e39f9a73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cc6f9c3c763acf9b012c571851dcf3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0cc6f9c3c763acf9b012c571851dcf3a">XI3C_INTR_HJ_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga0cc6f9c3c763acf9b012c571851dcf3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 8 - Hot join.  <a href="group___overview.html#ga0cc6f9c3c763acf9b012c571851dcf3a">More...</a><br/></td></tr>
<tr class="separator:ga0cc6f9c3c763acf9b012c571851dcf3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga844df14294ccf0b9c2057b64e9be57ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga844df14294ccf0b9c2057b64e9be57ac">XI3C_INTR_CTRL_ROLE_REQUEST_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga844df14294ccf0b9c2057b64e9be57ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 9 - Received control role request.  <a href="group___overview.html#ga844df14294ccf0b9c2057b64e9be57ac">More...</a><br/></td></tr>
<tr class="separator:ga844df14294ccf0b9c2057b64e9be57ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69a1d41376d8e223e7d8468a50196b03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga69a1d41376d8e223e7d8468a50196b03">XI3C_INTR_ERROR_TYPE_CE3_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga69a1d41376d8e223e7d8468a50196b03"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role.  <a href="group___overview.html#ga69a1d41376d8e223e7d8468a50196b03">More...</a><br/></td></tr>
<tr class="separator:ga69a1d41376d8e223e7d8468a50196b03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga685b9e09fe59849441299b87aeaa1251"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga685b9e09fe59849441299b87aeaa1251">XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga685b9e09fe59849441299b87aeaa1251"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 11 - Received ACK on controller role request back.  <a href="group___overview.html#ga685b9e09fe59849441299b87aeaa1251">More...</a><br/></td></tr>
<tr class="separator:ga685b9e09fe59849441299b87aeaa1251"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga11f5367ba0a41f97993c47cff79ad7f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga11f5367ba0a41f97993c47cff79ad7f4">XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga11f5367ba0a41f97993c47cff79ad7f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 12 - Read Fifo almost Full.  <a href="group___overview.html#ga11f5367ba0a41f97993c47cff79ad7f4">More...</a><br/></td></tr>
<tr class="separator:ga11f5367ba0a41f97993c47cff79ad7f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1c7c16b87d0571f53a041676f2c63a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf1c7c16b87d0571f53a041676f2c63a7">XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gaf1c7c16b87d0571f53a041676f2c63a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 13 - CMD FIFO empty.  <a href="group___overview.html#gaf1c7c16b87d0571f53a041676f2c63a7">More...</a><br/></td></tr>
<tr class="separator:gaf1c7c16b87d0571f53a041676f2c63a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf48010016e4266ae11f968791685435"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacf48010016e4266ae11f968791685435">XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gacf48010016e4266ae11f968791685435"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 14 - Write FIFO empty.  <a href="group___overview.html#gacf48010016e4266ae11f968791685435">More...</a><br/></td></tr>
<tr class="separator:gacf48010016e4266ae11f968791685435"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb3daf54b287d6bde50bd16b2ce6b28d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafb3daf54b287d6bde50bd16b2ce6b28d">XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:gafb3daf54b287d6bde50bd16b2ce6b28d"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 15 - Read FIFO empty.  <a href="group___overview.html#gafb3daf54b287d6bde50bd16b2ce6b28d">More...</a><br/></td></tr>
<tr class="separator:gafb3daf54b287d6bde50bd16b2ce6b28d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab12a89030f0016bebe64fac8878cc57f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XI3c_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gab12a89030f0016bebe64fac8878cc57f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read an I3C register.  <a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">More...</a><br/></td></tr>
<tr class="separator:gab12a89030f0016bebe64fac8878cc57f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d1adc84977bc35bde5d82bb4a874d6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XI3c_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:ga6d1adc84977bc35bde5d82bb4a874d6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write an I3C register.  <a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">More...</a><br/></td></tr>
<tr class="separator:ga6d1adc84977bc35bde5d82bb4a874d6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a979344e276171bf0bf87eb27c7ffd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga0a979344e276171bf0bf87eb27c7ffd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read WR FIFO LEVEL.  <a href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">More...</a><br/></td></tr>
<tr class="separator:ga0a979344e276171bf0bf87eb27c7ffd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e01aa9fa4c727ed5fbd43736b05fad7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5e01aa9fa4c727ed5fbd43736b05fad7">XI3c_CmdFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga5e01aa9fa4c727ed5fbd43736b05fad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read CMD FIFO LEVEL.  <a href="group___overview.html#ga5e01aa9fa4c727ed5fbd43736b05fad7">More...</a><br/></td></tr>
<tr class="separator:ga5e01aa9fa4c727ed5fbd43736b05fad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7ca28d237412cebb19bb2d5bde6eae6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6">XI3c_RdFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:gac7ca28d237412cebb19bb2d5bde6eae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read RD FIFO LEVEL.  <a href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6">More...</a><br/></td></tr>
<tr class="separator:gac7ca28d237412cebb19bb2d5bde6eae6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf68a808c2f04670d1b37a874ab0368dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf68a808c2f04670d1b37a874ab0368dd">XI3c_RespFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf68a808c2f04670d1b37a874ab0368dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read RESP FIFO LEVEL.  <a href="group___overview.html#gaf68a808c2f04670d1b37a874ab0368dd">More...</a><br/></td></tr>
<tr class="separator:gaf68a808c2f04670d1b37a874ab0368dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga502dee04797d325155788141fa7db242"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga502dee04797d325155788141fa7db242">XI3c_RxFifoNotEmpty</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga502dee04797d325155788141fa7db242"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check Read FIFO empty status.  <a href="group___overview.html#ga502dee04797d325155788141fa7db242">More...</a><br/></td></tr>
<tr class="separator:ga502dee04797d325155788141fa7db242"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0836e481b2a27d2f3b7f2992d7c1be0f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0836e481b2a27d2f3b7f2992d7c1be0f">XI3c_RespFifoNotEmpty</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga0836e481b2a27d2f3b7f2992d7c1be0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check Response FIFO empty status.  <a href="group___overview.html#ga0836e481b2a27d2f3b7f2992d7c1be0f">More...</a><br/></td></tr>
<tr class="separator:ga0836e481b2a27d2f3b7f2992d7c1be0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f2003a310655cbf699490aca1b1b460"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">XI3c_EnableREInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga4f2003a310655cbf699490aca1b1b460"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Raising edge interrupts.  <a href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">More...</a><br/></td></tr>
<tr class="separator:ga4f2003a310655cbf699490aca1b1b460"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03622c20170a3203409c18ac0efcd1e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03622c20170a3203409c18ac0efcd1e7">XI3c_EnableFEInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga03622c20170a3203409c18ac0efcd1e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Faling edge interrupts.  <a href="group___overview.html#ga03622c20170a3203409c18ac0efcd1e7">More...</a><br/></td></tr>
<tr class="separator:ga03622c20170a3203409c18ac0efcd1e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa44c7fcb3f5568047c20e274f1e0de37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa44c7fcb3f5568047c20e274f1e0de37">XI3c_DisableREInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:gaa44c7fcb3f5568047c20e274f1e0de37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable raising edge interrupts.  <a href="group___overview.html#gaa44c7fcb3f5568047c20e274f1e0de37">More...</a><br/></td></tr>
<tr class="separator:gaa44c7fcb3f5568047c20e274f1e0de37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e84fcb954a3294f93ef7c65d74c22d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6e84fcb954a3294f93ef7c65d74c22d8">XI3c_DisableFEInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga6e84fcb954a3294f93ef7c65d74c22d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable faling edge interrupts.  <a href="group___overview.html#ga6e84fcb954a3294f93ef7c65d74c22d8">More...</a><br/></td></tr>
<tr class="separator:ga6e84fcb954a3294f93ef7c65d74c22d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab22c206fca9f2352b27b6514e5076039"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab22c206fca9f2352b27b6514e5076039">XI3c_DisableAllREInterrupts</a>(BaseAddress)</td></tr>
<tr class="memdesc:gab22c206fca9f2352b27b6514e5076039"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all raising edge interrupts.  <a href="group___overview.html#gab22c206fca9f2352b27b6514e5076039">More...</a><br/></td></tr>
<tr class="separator:gab22c206fca9f2352b27b6514e5076039"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a1f816187914a7db17f86e3a9570a04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a1f816187914a7db17f86e3a9570a04">XI3c_DisableAllFEInterrupts</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga0a1f816187914a7db17f86e3a9570a04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all faling edge interrupts.  <a href="group___overview.html#ga0a1f816187914a7db17f86e3a9570a04">More...</a><br/></td></tr>
<tr class="separator:ga0a1f816187914a7db17f86e3a9570a04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2577bc2333d12a6bd75e2a79442f90bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd">XI3c_FillSlaveSendCount</a>(InstancePtr, ByteCount)</td></tr>
<tr class="memdesc:ga2577bc2333d12a6bd75e2a79442f90bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fill Slave send byte count value.  <a href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd">More...</a><br/></td></tr>
<tr class="separator:ga2577bc2333d12a6bd75e2a79442f90bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93e2ff09fe04f9e588ca08ae03f9ae37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga93e2ff09fe04f9e588ca08ae03f9ae37">XI3c_ClearGrpAddr</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga93e2ff09fe04f9e588ca08ae03f9ae37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the group address of target.  <a href="group___overview.html#ga93e2ff09fe04f9e588ca08ae03f9ae37">More...</a><br/></td></tr>
<tr class="separator:ga93e2ff09fe04f9e588ca08ae03f9ae37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7acb6d781c60d402811ddc9f45552229"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7acb6d781c60d402811ddc9f45552229">XI3c_GetMWL</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga7acb6d781c60d402811ddc9f45552229"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Maximum write length.  <a href="group___overview.html#ga7acb6d781c60d402811ddc9f45552229">More...</a><br/></td></tr>
<tr class="separator:ga7acb6d781c60d402811ddc9f45552229"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab50db6a1880449022a970ccb4d8a6d25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab50db6a1880449022a970ccb4d8a6d25">XI3c_GetMRL</a>(InstancePtr)</td></tr>
<tr class="memdesc:gab50db6a1880449022a970ccb4d8a6d25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Maximum read length.  <a href="group___overview.html#gab50db6a1880449022a970ccb4d8a6d25">More...</a><br/></td></tr>
<tr class="separator:gab50db6a1880449022a970ccb4d8a6d25"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
